********************************
* Copyright:                   *
* Vishay Intertechnology, Inc. *
********************************
*Jul 14, 2014
*ECN S14-1394, Rev. B
*File Name: SiR804DP_PS.txt and SiR804DP_PS.lib
*This document is intended as a SPICE modeling guideline and does not
*constitute a commercial product datasheet.  Designers should refer to the
*appropriate datasheet of the same number for guaranteed specification
*limits.
.SUBCKT SiR804DP D G S 
M1 3 GX S S NMOS W= 4906504u L= 0.25u 
M2 S GX S D PMOS W= 4906504u L= 2.382e-07 
R1 D 3 3.729e-03 TC=8.092e-03 1.713e-05 
CGS GX S 1.741e-09 
CGD GX D 7.177e-11 
RG G GY 2 
RTCV 100 S 1e6 TC=-8.396e-04 3.153e-06 
ETCV GX GY 100 200 1 
ITCV S 100 1u 
VTCV 200 S 1 
DBD S D DBD 
**************************************************************** 
.MODEL NMOS NMOS ( LEVEL = 3 TOX = 5e-8 
+ RS = 1.519e-03 KP = 1.1e-05 NSUB = 1.472e+17 
+ KAPPA = 5.68e-02 ETA = 8.131e-05 NFS = 5.173e+11 
+ LD = 0 IS = 0 TPG = 1) 
*************************************************************** 
.MODEL PMOS PMOS ( LEVEL = 3 TOX = 5e-8 
+NSUB = 1.385e+16 IS = 0 TPG = -1 ) 
**************************************************************** 
.MODEL DBD D ( 
+FC = 0.1 TT = 9.840e-09 T_MEASURED = 25 BV = 101 
+RS = 2.099e-03 N = 1.093e+00 IS = 2.209e-11 
+EG = 1.166e+00 XTI = 3.779e-01 TRS1 = 6.606e-04 
+CJO = 7.118e-09 VJ = 3.909e-01 M = 3.400e-01 ) 
.ENDS 
